As high-density packaging of integrated circuit devices of silicon semiconductors continues to make rapid advancements, higher quality of silicon wafers for the devices is increasingly in demand. That is, crystal defects such as dislocation causing an increase of leak current and a reduction of carrier lifetime are more and more restricted than before since circuit lines become even finer as the higher-density integration is made.
In general, in the manufacture of an epitaxial wafer, a single crystal silicon wafer forming a substrate is placed on a susceptor, the silicon wafer forming the substrate and peripheral components are cleaned, and the surface of the substrate is exposed to a silicon source such as silane or trichlorosilane at a temperature of about 800° C. or higher such that an epitaxial layer of silicon may be grown over the surface. After the epitaxial layer is grown to a predetermined thickness, the supply of a raw material gas is thereafter stopped, the silicon wafer with the epitaxial layer thereon is lowered in temperature and is removed out of a chamber, and the epitaxial wafer can be then fed to the next step. In these series of manufacturing steps, extreme caution is taken to avoid contamination and crystal defects such as dislocation.
Since the growth of the epitaxial layer is greatly affected by the temperature, the temperature control is of great importance. When a steep temperature gradient occurs between the main surface and the back surface of the silicon wafer, warpage of the silicon wafer may be caused. Even if the silicon wafer is not warped, crystal defects such as slip dislocation may be caused in the wafer. For this reason, in the case where the epitaxial layer is grown over the main surface of the silicon wafer, the drastic temperature drop is prevented by gradually supplying the raw material gas, and the output of high-frequency inductive heater to heat the susceptor is controlled such that the heat transfer from the susceptor to the silicon wafer may be regulated (for example, Japanese Unexamined Patent Application Publication No. 2002-16004).
On the other hand, a technology to prevent the slip dislocation from occurring is disclosed in which the heat treatment of the semiconductor wafer is conducted in a state that the temperature of a portion of the semiconductor wafer that comes in contact with a jig for supporting the semiconductor wafer is controlled to be 3 to 20° C. less than that of the center portion of the semiconductor wafer in a step of heat treating the semiconductor wafer at a predetermined temperature with an RTA apparatus in the semiconductor wafer manufacturing method (for example, Japanese Unexamined Patent Application Publication No. 2002-164300).